make and makefile

Thu, 26 Dec 2024 05:35:00 -0700

I am a C/C++ newbie, but occassionally I have to compile or build projects. Since make (and Makefiles) are quite prevalent and sometimes they have to be adjusted due to potential errors, I had to learn more about them and want to share my learning publicly here.

Building Blocks

First of all, what are the involved building blocks of make and Makefiles?

make:
- The GNU make utility. This is the executable that you actually run in order to execute a series of commands in order to modify files, typically compiling programs.
- If you run the program without specifying an explicit input file with the -f option, make will look for the makefiles GNUmakefile, makefile, and Makefile, in that order.
- make updates a target if it depends on prerequisite files that have been modified since the target was last modified, or if the target does not exist.
makefile:
- This is the input file for the make utility and consists of a series of instructions how to modify files.
- A makefile can contain one or more rules.
rule:
- A rule consists of one or more targets, prerequisites and commands.
target:
- A target is a file name and typically, there is only one per rule.
prerequisite:
- The prerequisites are file names, separated by spaces. These files need to exist before the commands for the target are run. These are also called dependencies.
command:
- The commands are a series of steps typically to make the target. They need to start with a tab character, not spaces.

The general format of a Makefile is as follows:

Makefile on soffensive blog

make and makefile

Building Blocks